This website requires JavaScript.
Explore
Help
Register
Sign in
Techwizz
/
kernel-fxtec-pro1x
Watch
1
Star
0
Fork
You've already forked kernel-fxtec-pro1x
0
Code
Issues
Pull requests
Projects
Releases
Packages
Wiki
Activity
29020c9a40
kernel-fxtec-pro1x
/
drivers
/
clk
/
mvebu
/
Kconfig
9 lines
105 B
Text
Raw
Normal View
History
Unescape
Escape
clk: mvebu: add mvebu core clocks. This driver allows to provide DT clocks for core clocks found on Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and ratios are determined by decoding the Sample-At-Reset registers. Although technically correct, using a divider of 0 will lead to div_by_zero panic. Let's use a ratio of 0/1 instead to fail later with a zero clock. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
2012-11-17 07:22:22 -07:00
config MVEBU_CLK_CORE
bool
clk: mvebu: add armada-370-xp CPU specific clocks Add Armada 370/XP specific CPU clocks Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2012-11-17 07:22:23 -07:00
config MVEBU_CLK_CPU
bool
clk: mvebu: add clock gating control provider for DT This driver allows to provide DT clocks for clock gates found on Marvell Dove and Kirkwood SoCs. The clock gates are referenced by the phandle index of the corresponding bit in the clock gating control register to ease lookup in the datasheet. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2012-11-17 07:22:26 -07:00
config MVEBU_CLK_GATING
bool
Reference in a new issue
Copy permalink