2005-04-16 16:20:36 -06:00
|
|
|
/*******************************************************************************
|
|
|
|
|
|
|
|
|
|
|
2006-05-26 10:38:10 -06:00
|
|
|
Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
|
This program is free software; you can redistribute it and/or modify it
|
|
|
|
|
under the terms of the GNU General Public License as published by the Free
|
|
|
|
|
Software Foundation; either version 2 of the License, or (at your option)
|
|
|
|
|
any later version.
|
|
|
|
|
|
|
|
|
|
This program is distributed in the hope that it will be useful, but WITHOUT
|
|
|
|
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
|
|
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
|
|
|
more details.
|
|
|
|
|
|
|
|
|
|
You should have received a copy of the GNU General Public License along with
|
|
|
|
|
this program; if not, write to the Free Software Foundation, Inc., 59
|
|
|
|
|
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
|
|
|
|
|
|
|
|
|
The full GNU General Public License is included in this distribution in the
|
|
|
|
|
file called LICENSE.
|
|
|
|
|
|
|
|
|
|
Contact Information:
|
|
|
|
|
Linux NICS <linux.nics@intel.com>
|
|
|
|
|
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
|
|
|
|
|
|
|
|
|
*******************************************************************************/
|
|
|
|
|
|
|
|
|
|
/* glue for the OS independent part of ixgb
|
|
|
|
|
* includes register access macros
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifndef _IXGB_OSDEP_H_
|
|
|
|
|
#define _IXGB_OSDEP_H_
|
|
|
|
|
|
|
|
|
|
#include <linux/types.h>
|
|
|
|
|
#include <linux/pci.h>
|
|
|
|
|
#include <linux/delay.h>
|
|
|
|
|
#include <asm/io.h>
|
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
|
#include <linux/sched.h>
|
|
|
|
|
|
|
|
|
|
#ifndef msec_delay
|
|
|
|
|
#define msec_delay(x) do { if(in_interrupt()) { \
|
|
|
|
|
/* Don't mdelay in interrupt context! */ \
|
|
|
|
|
BUG(); \
|
|
|
|
|
} else { \
|
2005-04-28 20:05:12 -06:00
|
|
|
msleep(x); \
|
2005-04-16 16:20:36 -06:00
|
|
|
} } while(0)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define PCI_COMMAND_REGISTER PCI_COMMAND
|
|
|
|
|
#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
|
|
|
|
|
|
|
|
|
|
typedef enum {
|
|
|
|
|
#undef FALSE
|
|
|
|
|
FALSE = 0,
|
|
|
|
|
#undef TRUE
|
|
|
|
|
TRUE = 1
|
|
|
|
|
} boolean_t;
|
|
|
|
|
|
|
|
|
|
#undef ASSERT
|
|
|
|
|
#define ASSERT(x) if(!(x)) BUG()
|
|
|
|
|
#define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B)
|
|
|
|
|
|
|
|
|
|
#ifdef DBG
|
|
|
|
|
#define DEBUGOUT(S) printk(KERN_DEBUG S "\n")
|
|
|
|
|
#define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A)
|
|
|
|
|
#else
|
|
|
|
|
#define DEBUGOUT(S)
|
|
|
|
|
#define DEBUGOUT1(S, A...)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define DEBUGFUNC(F) DEBUGOUT(F)
|
|
|
|
|
#define DEBUGOUT2 DEBUGOUT1
|
|
|
|
|
#define DEBUGOUT3 DEBUGOUT2
|
|
|
|
|
#define DEBUGOUT7 DEBUGOUT3
|
|
|
|
|
|
|
|
|
|
#define IXGB_WRITE_REG(a, reg, value) ( \
|
|
|
|
|
writel((value), ((a)->hw_addr + IXGB_##reg)))
|
|
|
|
|
|
|
|
|
|
#define IXGB_READ_REG(a, reg) ( \
|
|
|
|
|
readl((a)->hw_addr + IXGB_##reg))
|
|
|
|
|
|
|
|
|
|
#define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \
|
|
|
|
|
writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2))))
|
|
|
|
|
|
|
|
|
|
#define IXGB_READ_REG_ARRAY(a, reg, offset) ( \
|
|
|
|
|
readl((a)->hw_addr + IXGB_##reg + ((offset) << 2)))
|
|
|
|
|
|
|
|
|
|
#define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS)
|
|
|
|
|
|
|
|
|
|
#define IXGB_MEMCPY memcpy
|
|
|
|
|
|
|
|
|
|
#endif /* _IXGB_OSDEP_H_ */
|
