2009-04-02 19:49:22 -06:00
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/*
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2005-04-16 16:20:36 -06:00
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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2006-03-27 12:52:14 -07:00
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* Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
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2005-04-16 16:20:36 -06:00
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* Copyright (C) 1999 SuSE GmbH Nuernberg
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* Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
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*
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* Cache and TLB management
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*
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#include <linux/pagemap.h>
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Detach sched.h from mm.h
First thing mm.h does is including sched.h solely for can_do_mlock() inline
function which has "current" dereference inside. By dealing with can_do_mlock()
mm.h can be detached from sched.h which is good. See below, why.
This patch
a) removes unconditional inclusion of sched.h from mm.h
b) makes can_do_mlock() normal function in mm/mlock.c
c) exports can_do_mlock() to not break compilation
d) adds sched.h inclusions back to files that were getting it indirectly.
e) adds less bloated headers to some files (asm/signal.h, jiffies.h) that were
getting them indirectly
Net result is:
a) mm.h users would get less code to open, read, preprocess, parse, ... if
they don't need sched.h
b) sched.h stops being dependency for significant number of files:
on x86_64 allmodconfig touching sched.h results in recompile of 4083 files,
after patch it's only 3744 (-8.3%).
Cross-compile tested on
all arm defconfigs, all mips defconfigs, all powerpc defconfigs,
alpha alpha-up
arm
i386 i386-up i386-defconfig i386-allnoconfig
ia64 ia64-up
m68k
mips
parisc parisc-up
powerpc powerpc-up
s390 s390-up
sparc sparc-up
sparc64 sparc64-up
um-x86_64
x86_64 x86_64-up x86_64-defconfig x86_64-allnoconfig
as well as my two usual configs.
Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-20 15:22:52 -06:00
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#include <linux/sched.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/pdc.h>
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/processor.h>
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2005-10-21 20:44:14 -06:00
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#include <asm/sections.h>
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2005-04-16 16:20:36 -06:00
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2006-01-10 18:35:03 -07:00
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int split_tlb __read_mostly;
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int dcache_stride __read_mostly;
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int icache_stride __read_mostly;
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2005-04-16 16:20:36 -06:00
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EXPORT_SYMBOL(dcache_stride);
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/* On some machines (e.g. ones with the Merced bus), there can be
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* only a single PxTLB broadcast at a time; this must be guaranteed
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* by software. We put a spinlock around all TLB flushes to
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* ensure this.
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*/
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DEFINE_SPINLOCK(pa_tlb_lock);
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2006-01-10 18:35:03 -07:00
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struct pdc_cache_info cache_info __read_mostly;
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2005-04-16 16:20:36 -06:00
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#ifndef CONFIG_PA20
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2006-01-10 18:35:03 -07:00
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static struct pdc_btlb_info btlb_info __read_mostly;
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2005-04-16 16:20:36 -06:00
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#endif
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#ifdef CONFIG_SMP
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void
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flush_data_cache(void)
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{
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2008-05-09 01:39:44 -06:00
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on_each_cpu(flush_data_cache_local, NULL, 1);
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2005-04-16 16:20:36 -06:00
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}
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void
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flush_instruction_cache(void)
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{
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2008-05-09 01:39:44 -06:00
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on_each_cpu(flush_instruction_cache_local, NULL, 1);
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2005-04-16 16:20:36 -06:00
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}
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#endif
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void
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flush_cache_all_local(void)
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{
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2006-01-10 18:47:49 -07:00
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flush_instruction_cache_local(NULL);
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flush_data_cache_local(NULL);
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2005-04-16 16:20:36 -06:00
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}
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EXPORT_SYMBOL(flush_cache_all_local);
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void
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MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies. We do this via make_coherent() by making the pages
uncacheable.
This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().
Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():
On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
to construct a pointer to the pte again. Passing a pte_t * is much
more elegant. Maybe we might even replace the pte argument with the
pte_t?
Ben Herrenschmidt would also like the pte pointer for PowerPC:
Passing the ptep in there is exactly what I want. I want that
-instead- of the PTE value, because I have issue on some ppc cases,
for I$/D$ coherency, where set_pte_at() may decide to mask out the
_PAGE_EXEC.
So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.
Includes a fix from Stephen Rothwell:
sparc: fix fallout from update_mmu_cache API change
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-18 09:40:18 -07:00
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update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
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2005-04-16 16:20:36 -06:00
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{
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MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies. We do this via make_coherent() by making the pages
uncacheable.
This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().
Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():
On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
to construct a pointer to the pte again. Passing a pte_t * is much
more elegant. Maybe we might even replace the pte argument with the
pte_t?
Ben Herrenschmidt would also like the pte pointer for PowerPC:
Passing the ptep in there is exactly what I want. I want that
-instead- of the PTE value, because I have issue on some ppc cases,
for I$/D$ coherency, where set_pte_at() may decide to mask out the
_PAGE_EXEC.
So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.
Includes a fix from Stephen Rothwell:
sparc: fix fallout from update_mmu_cache API change
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-18 09:40:18 -07:00
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struct page *page = pte_page(*ptep);
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2005-04-16 16:20:36 -06:00
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if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
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test_bit(PG_dcache_dirty, &page->flags)) {
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2006-03-22 09:42:04 -07:00
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flush_kernel_dcache_page(page);
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2005-04-16 16:20:36 -06:00
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clear_bit(PG_dcache_dirty, &page->flags);
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2006-08-23 10:00:04 -06:00
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} else if (parisc_requires_coherency())
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flush_kernel_dcache_page(page);
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2005-04-16 16:20:36 -06:00
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}
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void
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show_cache_info(struct seq_file *m)
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{
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2006-06-14 14:26:25 -06:00
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char buf[32];
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2005-04-16 16:20:36 -06:00
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seq_printf(m, "I-cache\t\t: %ld KB\n",
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cache_info.ic_size/1024 );
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2007-01-23 13:24:20 -07:00
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if (cache_info.dc_loop != 1)
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2006-06-14 14:26:25 -06:00
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snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
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seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
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2005-04-16 16:20:36 -06:00
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cache_info.dc_size/1024,
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(cache_info.dc_conf.cc_wt ? "WT":"WB"),
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(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
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2006-06-14 14:26:25 -06:00
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((cache_info.dc_loop == 1) ? "direct mapped" : buf));
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2005-04-16 16:20:36 -06:00
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seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
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cache_info.it_size,
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cache_info.dt_size,
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cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
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);
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#ifndef CONFIG_PA20
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/* BTLB - Block TLB */
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if (btlb_info.max_size==0) {
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seq_printf(m, "BTLB\t\t: not supported\n" );
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} else {
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seq_printf(m,
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"BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
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"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
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"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
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btlb_info.max_size, (int)4096,
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btlb_info.max_size>>8,
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btlb_info.fixed_range_info.num_i,
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btlb_info.fixed_range_info.num_d,
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btlb_info.fixed_range_info.num_comb,
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btlb_info.variable_range_info.num_i,
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btlb_info.variable_range_info.num_d,
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btlb_info.variable_range_info.num_comb
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);
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}
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#endif
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}
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void __init
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parisc_cache_init(void)
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{
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if (pdc_cache_info(&cache_info) < 0)
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panic("parisc_cache_init: pdc_cache_info failed");
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#if 0
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printk("ic_size %lx dc_size %lx it_size %lx\n",
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cache_info.ic_size,
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cache_info.dc_size,
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cache_info.it_size);
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printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
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cache_info.dc_base,
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cache_info.dc_stride,
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cache_info.dc_count,
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cache_info.dc_loop);
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printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
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*(unsigned long *) (&cache_info.dc_conf),
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cache_info.dc_conf.cc_alias,
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cache_info.dc_conf.cc_block,
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cache_info.dc_conf.cc_line,
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cache_info.dc_conf.cc_shift);
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2006-06-14 14:26:25 -06:00
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printk(" wt %d sh %d cst %d hv %d\n",
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2005-04-16 16:20:36 -06:00
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cache_info.dc_conf.cc_wt,
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cache_info.dc_conf.cc_sh,
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cache_info.dc_conf.cc_cst,
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2006-06-14 14:26:25 -06:00
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cache_info.dc_conf.cc_hv);
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2005-04-16 16:20:36 -06:00
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printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
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cache_info.ic_base,
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cache_info.ic_stride,
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cache_info.ic_count,
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cache_info.ic_loop);
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printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
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*(unsigned long *) (&cache_info.ic_conf),
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cache_info.ic_conf.cc_alias,
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cache_info.ic_conf.cc_block,
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cache_info.ic_conf.cc_line,
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cache_info.ic_conf.cc_shift);
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2006-06-14 14:26:25 -06:00
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printk(" wt %d sh %d cst %d hv %d\n",
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2005-04-16 16:20:36 -06:00
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cache_info.ic_conf.cc_wt,
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cache_info.ic_conf.cc_sh,
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cache_info.ic_conf.cc_cst,
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2006-06-14 14:26:25 -06:00
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cache_info.ic_conf.cc_hv);
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2005-04-16 16:20:36 -06:00
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2010-02-06 10:47:14 -07:00
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printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n",
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2005-04-16 16:20:36 -06:00
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cache_info.dt_conf.tc_sh,
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cache_info.dt_conf.tc_page,
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cache_info.dt_conf.tc_cst,
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cache_info.dt_conf.tc_aid,
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cache_info.dt_conf.tc_pad1);
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2010-02-06 10:47:14 -07:00
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printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n",
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2005-04-16 16:20:36 -06:00
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cache_info.it_conf.tc_sh,
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cache_info.it_conf.tc_page,
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cache_info.it_conf.tc_cst,
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cache_info.it_conf.tc_aid,
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cache_info.it_conf.tc_pad1);
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#endif
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split_tlb = 0;
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if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
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if (cache_info.dt_conf.tc_sh == 2)
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printk(KERN_WARNING "Unexpected TLB configuration. "
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"Will flush I/D separately (could be optimized).\n");
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split_tlb = 1;
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}
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/* "New and Improved" version from Jim Hull
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* (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
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2005-10-21 20:44:14 -06:00
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* The following CAFL_STRIDE is an optimized version, see
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* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
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* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
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2005-04-16 16:20:36 -06:00
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*/
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#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
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dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
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icache_stride = CAFL_STRIDE(cache_info.ic_conf);
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#undef CAFL_STRIDE
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#ifndef CONFIG_PA20
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if (pdc_btlb_info(&btlb_info) < 0) {
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memset(&btlb_info, 0, sizeof btlb_info);
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}
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#endif
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if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
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PDC_MODEL_NVA_UNSUPPORTED) {
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printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
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#if 0
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panic("SMP kernel required to avoid non-equivalent aliasing");
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#endif
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}
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}
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void disable_sr_hashing(void)
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{
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2006-06-16 16:20:00 -06:00
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int srhash_type, retval;
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unsigned long space_bits;
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2005-04-16 16:20:36 -06:00
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switch (boot_cpu_data.cpu_type) {
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case pcx: /* We shouldn't get this far. setup.c should prevent it. */
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BUG();
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return;
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case pcxs:
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case pcxt:
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case pcxt_:
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srhash_type = SRHASH_PCXST;
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break;
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case pcxl:
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srhash_type = SRHASH_PCXL;
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break;
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case pcxl2: /* pcxl2 doesn't support space register hashing */
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return;
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default: /* Currently all PA2.0 machines use the same ins. sequence */
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srhash_type = SRHASH_PA20;
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break;
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}
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disable_sr_hashing_asm(srhash_type);
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2006-06-16 16:20:00 -06:00
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retval = pdc_spaceid_bits(&space_bits);
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|
|
/* If this procedure isn't implemented, don't panic. */
|
|
|
|
if (retval < 0 && retval != PDC_BAD_OPTION)
|
|
|
|
panic("pdc_spaceid_bits call failed.\n");
|
|
|
|
if (space_bits != 0)
|
|
|
|
panic("SpaceID hashing is still on!\n");
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2006-12-12 06:51:54 -07:00
|
|
|
/* Simple function to work out if we have an existing address translation
|
|
|
|
* for a user space vma. */
|
|
|
|
static inline int translation_exists(struct vm_area_struct *vma,
|
|
|
|
unsigned long addr, unsigned long pfn)
|
|
|
|
{
|
|
|
|
pgd_t *pgd = pgd_offset(vma->vm_mm, addr);
|
|
|
|
pmd_t *pmd;
|
|
|
|
pte_t pte;
|
|
|
|
|
|
|
|
if(pgd_none(*pgd))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
pmd = pmd_offset(pgd, addr);
|
|
|
|
if(pmd_none(*pmd) || pmd_bad(*pmd))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* We cannot take the pte lock here: flush_cache_page is usually
|
|
|
|
* called with pte lock already held. Whereas flush_dcache_page
|
|
|
|
* takes flush_dcache_mmap_lock, which is lower in the hierarchy:
|
|
|
|
* the vma itself is secure, but the pte might come or go racily.
|
|
|
|
*/
|
|
|
|
pte = *pte_offset_map(pmd, addr);
|
|
|
|
/* But pte_unmap() does nothing on this architecture */
|
|
|
|
|
|
|
|
/* Filter out coincidental file entries and swap entries */
|
|
|
|
if (!(pte_val(pte) & (_PAGE_FLUSH|_PAGE_PRESENT)))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return pte_pfn(pte) == pfn;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Private function to flush a page from the cache of a non-current
|
|
|
|
* process. cr25 contains the Page Directory of the current user
|
|
|
|
* process; we're going to hijack both it and the user space %sr3 to
|
|
|
|
* temporarily make the non-current process current. We have to do
|
|
|
|
* this because cache flushing may cause a non-access tlb miss which
|
|
|
|
* the handlers have to fill in from the pgd of the non-current
|
|
|
|
* process. */
|
|
|
|
static inline void
|
|
|
|
flush_user_cache_page_non_current(struct vm_area_struct *vma,
|
|
|
|
unsigned long vmaddr)
|
|
|
|
{
|
|
|
|
/* save the current process space and pgd */
|
|
|
|
unsigned long space = mfsp(3), pgd = mfctl(25);
|
|
|
|
|
2008-02-03 07:58:20 -07:00
|
|
|
/* we don't mind taking interrupts since they may not
|
2006-12-12 06:51:54 -07:00
|
|
|
* do anything with user space, but we can't
|
|
|
|
* be preempted here */
|
|
|
|
preempt_disable();
|
|
|
|
|
|
|
|
/* make us current */
|
|
|
|
mtctl(__pa(vma->vm_mm->pgd), 25);
|
|
|
|
mtsp(vma->vm_mm->context, 3);
|
|
|
|
|
|
|
|
flush_user_dcache_page(vmaddr);
|
|
|
|
if(vma->vm_flags & VM_EXEC)
|
|
|
|
flush_user_icache_page(vmaddr);
|
|
|
|
|
|
|
|
/* put the old current process back */
|
|
|
|
mtsp(space, 3);
|
|
|
|
mtctl(pgd, 25);
|
|
|
|
preempt_enable();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr)
|
|
|
|
{
|
|
|
|
if (likely(vma->vm_mm->context == mfsp(3))) {
|
|
|
|
flush_user_dcache_page(vmaddr);
|
|
|
|
if (vma->vm_flags & VM_EXEC)
|
|
|
|
flush_user_icache_page(vmaddr);
|
|
|
|
} else {
|
|
|
|
flush_user_cache_page_non_current(vma, vmaddr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
void flush_dcache_page(struct page *page)
|
|
|
|
{
|
|
|
|
struct address_space *mapping = page_mapping(page);
|
|
|
|
struct vm_area_struct *mpnt;
|
|
|
|
struct prio_tree_iter iter;
|
|
|
|
unsigned long offset;
|
|
|
|
unsigned long addr;
|
|
|
|
pgoff_t pgoff;
|
|
|
|
unsigned long pfn = page_to_pfn(page);
|
|
|
|
|
|
|
|
|
|
|
|
if (mapping && !mapping_mapped(mapping)) {
|
|
|
|
set_bit(PG_dcache_dirty, &page->flags);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2006-03-22 09:42:04 -07:00
|
|
|
flush_kernel_dcache_page(page);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
if (!mapping)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
|
|
|
|
|
|
|
|
/* We have carefully arranged in arch_get_unmapped_area() that
|
|
|
|
* *any* mappings of a file are always congruently mapped (whether
|
|
|
|
* declared as MAP_PRIVATE or MAP_SHARED), so we only need
|
|
|
|
* to flush one address here for them all to become coherent */
|
|
|
|
|
|
|
|
flush_dcache_mmap_lock(mapping);
|
|
|
|
vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
|
|
|
|
offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
|
|
|
|
addr = mpnt->vm_start + offset;
|
|
|
|
|
|
|
|
/* Flush instructions produce non access tlb misses.
|
|
|
|
* On PA, we nullify these instructions rather than
|
|
|
|
* taking a page fault if the pte doesn't exist.
|
|
|
|
* This is just for speed. If the page translation
|
|
|
|
* isn't there, there's no point exciting the
|
2005-10-29 19:16:36 -06:00
|
|
|
* nadtlb handler into a nullification frenzy.
|
|
|
|
*
|
|
|
|
* Make sure we really have this page: the private
|
2005-04-16 16:20:36 -06:00
|
|
|
* mappings may cover this area but have COW'd this
|
2005-10-29 19:16:36 -06:00
|
|
|
* particular page.
|
|
|
|
*/
|
|
|
|
if (translation_exists(mpnt, addr, pfn)) {
|
|
|
|
__flush_cache_page(mpnt, addr);
|
|
|
|
break;
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
flush_dcache_mmap_unlock(mapping);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(flush_dcache_page);
|
|
|
|
|
|
|
|
/* Defined in arch/parisc/kernel/pacache.S */
|
|
|
|
EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
|
2006-03-22 09:42:04 -07:00
|
|
|
EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
|
2005-04-16 16:20:36 -06:00
|
|
|
EXPORT_SYMBOL(flush_data_cache_local);
|
|
|
|
EXPORT_SYMBOL(flush_kernel_icache_range_asm);
|
|
|
|
|
|
|
|
void clear_user_page_asm(void *page, unsigned long vaddr)
|
|
|
|
{
|
2009-06-16 14:51:48 -06:00
|
|
|
unsigned long flags;
|
2005-04-16 16:20:36 -06:00
|
|
|
/* This function is implemented in assembly in pacache.S */
|
|
|
|
extern void __clear_user_page_asm(void *page, unsigned long vaddr);
|
|
|
|
|
2009-06-16 14:51:48 -06:00
|
|
|
purge_tlb_start(flags);
|
2005-04-16 16:20:36 -06:00
|
|
|
__clear_user_page_asm(page, vaddr);
|
2009-06-16 14:51:48 -06:00
|
|
|
purge_tlb_end(flags);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
|
2006-01-10 18:35:03 -07:00
|
|
|
int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2006-12-12 06:51:54 -07:00
|
|
|
void __init parisc_setup_cache_timing(void)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
unsigned long rangetime, alltime;
|
|
|
|
unsigned long size;
|
|
|
|
|
|
|
|
alltime = mfctl(16);
|
|
|
|
flush_data_cache();
|
|
|
|
alltime = mfctl(16) - alltime;
|
|
|
|
|
2005-10-21 20:44:14 -06:00
|
|
|
size = (unsigned long)(_end - _text);
|
2005-04-16 16:20:36 -06:00
|
|
|
rangetime = mfctl(16);
|
2005-10-21 20:44:14 -06:00
|
|
|
flush_kernel_dcache_range((unsigned long)_text, size);
|
2005-04-16 16:20:36 -06:00
|
|
|
rangetime = mfctl(16) - rangetime;
|
|
|
|
|
|
|
|
printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
|
|
|
|
alltime, size, rangetime);
|
|
|
|
|
|
|
|
/* Racy, but if we see an intermediate value, it's ok too... */
|
|
|
|
parisc_cache_flush_threshold = size * alltime / rangetime;
|
|
|
|
|
|
|
|
parisc_cache_flush_threshold = (parisc_cache_flush_threshold + L1_CACHE_BYTES - 1) &~ (L1_CACHE_BYTES - 1);
|
|
|
|
if (!parisc_cache_flush_threshold)
|
|
|
|
parisc_cache_flush_threshold = FLUSH_THRESHOLD;
|
|
|
|
|
2006-12-12 06:51:54 -07:00
|
|
|
if (parisc_cache_flush_threshold > cache_info.dc_size)
|
|
|
|
parisc_cache_flush_threshold = cache_info.dc_size;
|
|
|
|
|
2006-03-27 12:52:14 -07:00
|
|
|
printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
2006-08-23 10:00:04 -06:00
|
|
|
|
|
|
|
extern void purge_kernel_dcache_page(unsigned long);
|
|
|
|
extern void clear_user_page_asm(void *page, unsigned long vaddr);
|
|
|
|
|
2006-09-20 21:44:09 -06:00
|
|
|
void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
|
2006-08-23 10:00:04 -06:00
|
|
|
{
|
2009-06-16 14:51:48 -06:00
|
|
|
unsigned long flags;
|
|
|
|
|
2006-08-23 10:00:04 -06:00
|
|
|
purge_kernel_dcache_page((unsigned long)page);
|
2009-06-16 14:51:48 -06:00
|
|
|
purge_tlb_start(flags);
|
2006-08-23 10:00:04 -06:00
|
|
|
pdtlb_kernel(page);
|
2009-06-16 14:51:48 -06:00
|
|
|
purge_tlb_end(flags);
|
2006-08-23 10:00:04 -06:00
|
|
|
clear_user_page_asm(page, vaddr);
|
|
|
|
}
|
2006-09-20 21:44:09 -06:00
|
|
|
EXPORT_SYMBOL(clear_user_page);
|
2006-08-23 10:00:04 -06:00
|
|
|
|
|
|
|
void flush_kernel_dcache_page_addr(void *addr)
|
|
|
|
{
|
2009-06-16 14:51:48 -06:00
|
|
|
unsigned long flags;
|
|
|
|
|
2006-08-23 10:00:04 -06:00
|
|
|
flush_kernel_dcache_page_asm(addr);
|
2009-06-16 14:51:48 -06:00
|
|
|
purge_tlb_start(flags);
|
2006-08-23 10:00:04 -06:00
|
|
|
pdtlb_kernel(addr);
|
2009-06-16 14:51:48 -06:00
|
|
|
purge_tlb_end(flags);
|
2006-08-23 10:00:04 -06:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
|
|
|
|
|
|
|
|
void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
|
|
|
|
struct page *pg)
|
|
|
|
{
|
|
|
|
/* no coherency needed (all in kmap/kunmap) */
|
|
|
|
copy_user_page_asm(vto, vfrom);
|
|
|
|
if (!parisc_requires_coherency())
|
|
|
|
flush_kernel_dcache_page_asm(vto);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(copy_user_page);
|
|
|
|
|
|
|
|
#ifdef CONFIG_PA8X00
|
|
|
|
|
|
|
|
void kunmap_parisc(void *addr)
|
|
|
|
{
|
|
|
|
if (parisc_requires_coherency())
|
|
|
|
flush_kernel_dcache_page_addr(addr);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(kunmap_parisc);
|
|
|
|
#endif
|
2006-12-12 06:51:54 -07:00
|
|
|
|
|
|
|
void __flush_tlb_range(unsigned long sid, unsigned long start,
|
|
|
|
unsigned long end)
|
|
|
|
{
|
|
|
|
unsigned long npages;
|
|
|
|
|
|
|
|
npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
|
|
|
if (npages >= 512) /* 2MB of space: arbitrary, should be tuned */
|
|
|
|
flush_tlb_all();
|
|
|
|
else {
|
2009-06-16 14:51:48 -06:00
|
|
|
unsigned long flags;
|
|
|
|
|
2006-12-12 06:51:54 -07:00
|
|
|
mtsp(sid, 1);
|
2009-06-16 14:51:48 -06:00
|
|
|
purge_tlb_start(flags);
|
2006-12-12 06:51:54 -07:00
|
|
|
if (split_tlb) {
|
|
|
|
while (npages--) {
|
|
|
|
pdtlb(start);
|
|
|
|
pitlb(start);
|
|
|
|
start += PAGE_SIZE;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
while (npages--) {
|
|
|
|
pdtlb(start);
|
|
|
|
start += PAGE_SIZE;
|
|
|
|
}
|
|
|
|
}
|
2009-06-16 14:51:48 -06:00
|
|
|
purge_tlb_end(flags);
|
2006-12-12 06:51:54 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cacheflush_h_tmp_function(void *dummy)
|
|
|
|
{
|
|
|
|
flush_cache_all_local();
|
|
|
|
}
|
|
|
|
|
|
|
|
void flush_cache_all(void)
|
|
|
|
{
|
2008-05-09 01:39:44 -06:00
|
|
|
on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
|
2006-12-12 06:51:54 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void flush_cache_mm(struct mm_struct *mm)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
flush_cache_all();
|
|
|
|
#else
|
|
|
|
flush_cache_all_local();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
flush_user_dcache_range(unsigned long start, unsigned long end)
|
|
|
|
{
|
|
|
|
if ((end - start) < parisc_cache_flush_threshold)
|
|
|
|
flush_user_dcache_range_asm(start,end);
|
|
|
|
else
|
|
|
|
flush_data_cache();
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
flush_user_icache_range(unsigned long start, unsigned long end)
|
|
|
|
{
|
|
|
|
if ((end - start) < parisc_cache_flush_threshold)
|
|
|
|
flush_user_icache_range_asm(start,end);
|
|
|
|
else
|
|
|
|
flush_instruction_cache();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void flush_cache_range(struct vm_area_struct *vma,
|
|
|
|
unsigned long start, unsigned long end)
|
|
|
|
{
|
|
|
|
int sr3;
|
|
|
|
|
2009-01-06 04:57:01 -07:00
|
|
|
BUG_ON(!vma->vm_mm->context);
|
2006-12-12 06:51:54 -07:00
|
|
|
|
|
|
|
sr3 = mfsp(3);
|
|
|
|
if (vma->vm_mm->context == sr3) {
|
|
|
|
flush_user_dcache_range(start,end);
|
|
|
|
flush_user_icache_range(start,end);
|
|
|
|
} else {
|
|
|
|
flush_cache_all();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
|
|
|
|
{
|
|
|
|
BUG_ON(!vma->vm_mm->context);
|
|
|
|
|
|
|
|
if (likely(translation_exists(vma, vmaddr, pfn)))
|
|
|
|
__flush_cache_page(vma, vmaddr);
|
|
|
|
|
|
|
|
}
|