usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 09:10:58 -06:00
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ccflags-$(CONFIG_USB_DWC3_DEBUG) := -DDEBUG
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ccflags-$(CONFIG_USB_DWC3_VERBOSE) += -DVERBOSE_DEBUG
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obj-$(CONFIG_USB_DWC3) += dwc3.o
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dwc3-y := core.o
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2011-10-12 05:08:26 -06:00
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dwc3-y += host.o
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2011-10-12 05:15:10 -06:00
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dwc3-y += gadget.o ep0.o
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2011-10-12 05:08:26 -06:00
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 09:10:58 -06:00
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ifneq ($(CONFIG_DEBUG_FS),)
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dwc3-y += debugfs.o
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endif
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##
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# Platform-specific glue layers go here
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#
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# NOTICE: Make sure your glue layer doesn't depend on anything
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# which is arch-specific and that it compiles on all situations.
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#
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# We want to keep this requirement in order to be able to compile
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# the entire driver (with all its glue layers) on several architectures
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# and make sure it compiles fine. This will also help with allmodconfig
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# and allyesconfig builds.
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#
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# The only exception is the PCI glue layer, but that's only because
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# PCI doesn't provide nops if CONFIG_PCI isn't enabled.
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##
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obj-$(CONFIG_USB_DWC3) += dwc3-omap.o
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ifneq ($(CONFIG_PCI),)
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obj-$(CONFIG_USB_DWC3) += dwc3-pci.o
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endif
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