comment unused cpu feature test code, align 512bits for AVX-512
This commit is contained in:
Tim Felgentreff
parent
89e8560cd2
commit
553d660d39
3 changed files with 92 additions and 92 deletions
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@ -145,8 +145,8 @@ int UTF8GetPrev(const std::string &text, int curpos);
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/*----------------------------------------------------------------------------
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-- SIMD support
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----------------------------------------------------------------------------*/
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bool supportsSSE2();
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bool supportsAVX();
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// bool supportsSSE2();
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// bool supportsAVX();
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void *aligned_malloc(size_t alignment, size_t size);
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void aligned_free(void *block);
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@ -260,19 +260,19 @@ void InitAStar(int mapWidth, int mapHeight)
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AStarMapMax = AStarMapWidth * AStarMapHeight;
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// align the matrix, the open set, and the cost to move cache
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// on 32-byte boundary, in case the memset/memmove operations
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// on 64-byte boundary, in case the memset/memmove operations
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// of the libc we're using has a 128/256/512bit SIMD vector
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// instruction branch, since we might be clearing 8M of
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// memory for a 2048x2048 map
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AStarMatrixSize = sizeof(Node) * AStarMapMax;
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AStarMatrix = (Node *)aligned_malloc(32, AStarMatrixSize);
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AStarMatrix = (Node *)aligned_malloc(64, AStarMatrixSize);
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memset(AStarMatrix, 0, AStarMatrixSize);
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OpenSetMaxSize = AStarMapMax / MAX_OPEN_SET_RATIO;
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OpenSet = (Open *)aligned_malloc(32, OpenSetMaxSize * sizeof(Open));
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OpenSet = (Open *)aligned_malloc(64, OpenSetMaxSize * sizeof(Open));
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CostMoveToCacheSize = sizeof(int32_t) * AStarMapMax;
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CostMoveToCache = (int32_t*)aligned_malloc(32, CostMoveToCacheSize);
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CostMoveToCache = (int32_t*)aligned_malloc(64, CostMoveToCacheSize);
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memset(CostMoveToCache, CacheNotSet, CostMoveToCacheSize);
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for (int i = 0; i < 9; ++i) {
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@ -503,110 +503,110 @@ void PrintOnStdOut(const char *format, ...)
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fflush(stdout);
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}
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/*----------------------------------------------------------------------------
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Check SSE/AVX support.
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This can detect the instruction support of
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SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, SSE5, and AVX.
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----------------------------------------------------------------------------*/
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// /*----------------------------------------------------------------------------
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// Check SSE/AVX support.
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// This can detect the instruction support of
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// SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, SSE5, and AVX.
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// ----------------------------------------------------------------------------*/
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#ifdef __GNUC__
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// #ifdef __GNUC__
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static void __cpuid(int* cpuinfo, int info)
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{
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__asm__ __volatile__(
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"xchg %%ebx, %%edi;"
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"cpuid;"
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"xchg %%ebx, %%edi;"
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:"=a" (cpuinfo[0]), "=D" (cpuinfo[1]), "=c" (cpuinfo[2]), "=d" (cpuinfo[3])
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:"0" (info)
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);
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}
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// static void __cpuid(int* cpuinfo, int info)
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// {
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// __asm__ __volatile__(
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// "xchg %%ebx, %%edi;"
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// "cpuid;"
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// "xchg %%ebx, %%edi;"
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// :"=a" (cpuinfo[0]), "=D" (cpuinfo[1]), "=c" (cpuinfo[2]), "=d" (cpuinfo[3])
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// :"0" (info)
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// );
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// }
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static unsigned long long _xgetbv(unsigned int index)
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{
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unsigned int eax, edx;
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__asm__ __volatile__(
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"xgetbv;"
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: "=a" (eax), "=d"(edx)
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: "c" (index)
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);
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return ((unsigned long long)edx << 32) | eax;
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}
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// static unsigned long long _xgetbv(unsigned int index)
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// {
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// unsigned int eax, edx;
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// __asm__ __volatile__(
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// "xgetbv;"
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// : "=a" (eax), "=d"(edx)
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// : "c" (index)
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// );
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// return ((unsigned long long)edx << 32) | eax;
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// }
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#endif
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// #endif
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struct SIMDSupport {
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bool sseSupportted = false;
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bool sse2Supportted = false;
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bool sse3Supportted = false;
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bool ssse3Supportted = false;
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bool sse4_1Supportted = false;
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bool sse4_2Supportted = false;
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bool sse4aSupportted = false;
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bool sse5Supportted = false;
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bool avxSupportted = false;
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};
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// struct SIMDSupport {
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// bool sseSupportted = false;
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// bool sse2Supportted = false;
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// bool sse3Supportted = false;
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// bool ssse3Supportted = false;
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// bool sse4_1Supportted = false;
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// bool sse4_2Supportted = false;
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// bool sse4aSupportted = false;
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// bool sse5Supportted = false;
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// bool avxSupportted = false;
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// };
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static struct SIMDSupport checkSIMDSupport() {
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struct SIMDSupport s;
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// static struct SIMDSupport checkSIMDSupport() {
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// struct SIMDSupport s;
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int cpuinfo[4];
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__cpuid(cpuinfo, 1);
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// int cpuinfo[4];
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// __cpuid(cpuinfo, 1);
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// Check SSE, SSE2, SSE3, SSSE3, SSE4.1, and SSE4.2 support
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s.sseSupportted = cpuinfo[3] & (1 << 25) || false;
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s.sse2Supportted = cpuinfo[3] & (1 << 26) || false;
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s.sse3Supportted = cpuinfo[2] & (1 << 0) || false;
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s.ssse3Supportted = cpuinfo[2] & (1 << 9) || false;
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s.sse4_1Supportted = cpuinfo[2] & (1 << 19) || false;
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s.sse4_2Supportted = cpuinfo[2] & (1 << 20) || false;
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// // Check SSE, SSE2, SSE3, SSSE3, SSE4.1, and SSE4.2 support
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// s.sseSupportted = cpuinfo[3] & (1 << 25) || false;
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// s.sse2Supportted = cpuinfo[3] & (1 << 26) || false;
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// s.sse3Supportted = cpuinfo[2] & (1 << 0) || false;
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// s.ssse3Supportted = cpuinfo[2] & (1 << 9) || false;
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// s.sse4_1Supportted = cpuinfo[2] & (1 << 19) || false;
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// s.sse4_2Supportted = cpuinfo[2] & (1 << 20) || false;
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// ----------------------------------------------------------------------
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// // ----------------------------------------------------------------------
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// Check AVX support
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// References
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// http://software.intel.com/en-us/blogs/2011/04/14/is-avx-enabled/
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// http://insufficientlycomplicated.wordpress.com/2011/11/07/detecting-intel-advanced-vector-extensions-avx-in-visual-studio/
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// // Check AVX support
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// // References
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// // http://software.intel.com/en-us/blogs/2011/04/14/is-avx-enabled/
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// // http://insufficientlycomplicated.wordpress.com/2011/11/07/detecting-intel-advanced-vector-extensions-avx-in-visual-studio/
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s.avxSupportted = cpuinfo[2] & (1 << 28) || false;
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bool osxsaveSupported = cpuinfo[2] & (1 << 27) || false;
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if (osxsaveSupported && s.avxSupportted)
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{
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// _XCR_XFEATURE_ENABLED_MASK = 0
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unsigned long long xcrFeatureMask = _xgetbv(0);
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s.avxSupportted = (xcrFeatureMask & 0x6) == 0x6;
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}
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// s.avxSupportted = cpuinfo[2] & (1 << 28) || false;
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// bool osxsaveSupported = cpuinfo[2] & (1 << 27) || false;
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// if (osxsaveSupported && s.avxSupportted)
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// {
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// // _XCR_XFEATURE_ENABLED_MASK = 0
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// unsigned long long xcrFeatureMask = _xgetbv(0);
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// s.avxSupportted = (xcrFeatureMask & 0x6) == 0x6;
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// }
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// ----------------------------------------------------------------------
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// // ----------------------------------------------------------------------
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// Check SSE4a and SSE5 support
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// // Check SSE4a and SSE5 support
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// Get the number of valid extended IDs
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__cpuid(cpuinfo, 0x80000000);
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int numExtendedIds = cpuinfo[0];
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if (numExtendedIds >= 0x80000001)
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{
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__cpuid(cpuinfo, 0x80000001);
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s.sse4aSupportted = cpuinfo[2] & (1 << 6) || false;
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s.sse5Supportted = cpuinfo[2] & (1 << 11) || false;
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}
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// // Get the number of valid extended IDs
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// __cpuid(cpuinfo, 0x80000000);
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// int numExtendedIds = cpuinfo[0];
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// if (numExtendedIds >= 0x80000001)
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// {
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// __cpuid(cpuinfo, 0x80000001);
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// s.sse4aSupportted = cpuinfo[2] & (1 << 6) || false;
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// s.sse5Supportted = cpuinfo[2] & (1 << 11) || false;
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// }
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// ----------------------------------------------------------------------
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// // ----------------------------------------------------------------------
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return s;
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}
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// return s;
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// }
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bool supportsSSE2()
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{
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static struct SIMDSupport s = checkSIMDSupport();
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return s.sse2Supportted;
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}
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// bool supportsSSE2()
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// {
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// static struct SIMDSupport s = checkSIMDSupport();
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// return s.sse2Supportted;
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// }
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bool supportsAVX()
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{
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static struct SIMDSupport s = checkSIMDSupport();
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return s.avxSupportted;
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}
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// bool supportsAVX()
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// {
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// static struct SIMDSupport s = checkSIMDSupport();
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// return s.avxSupportted;
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// }
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void *aligned_malloc(size_t alignment, size_t size)
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{
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